1. Field of the Invention
The present invention relates to signal processing methods and signal processing devices, which perform signal processing on digital signals such as periodically sampled data representing musical tone signals, video signals, and the like.
This application claims priority on Japanese Patent Application No. 2006-77007, the content of which is incorporated herein by reference.
2. Description of the Related Art
Conventionally, various types of signal processing have been developed with respect to musical tone signals. For example, down-sampling is performed with respect to digital musical tone signals, which were already subjected to sampling with the sampling frequency fs of 485 kHz. Examples of down-sampling are described below.    (1) In the case of down-sampling in which the sampling frequency is reduced from 48 kHz to 24 kHz, fifty steps of operations are necessary for the low-pass filter (LPF) processing (which is needed for the down-sampling), wherein the output is produced once per 2 fs (where fs=48 kHz).    (2) In the case of down-sampling in which the sampling frequency is reduced from 48 kHz to 8 kHz, two hundred steps of operations are necessary for the low-pass filter processing, wherein the output is produced once per 6 fs (where fs=48 kHz).
The reason the number of steps of operations adapted to the low-pass filter processing changes in response to the down-sampling frequency is that the cutoff frequency must decrease as frequencies of signals become low.
The aforementioned processing can be realized by use of a digital signal processor (DSP) in accordance with the following methods.
A first method is that the amount of data processing needed for the down-sampling performed per each fs is represented by the maximum number of steps of operations. When the maximum number of operations is set to two hundred, 200 steps of operations are not performed in a distributed manner per 2 fs but are performed in a concentrated manner per 1 fs. FIG. 5 diagrammatically shows a time-related flow chart in accordance with this method, wherein the amount of data processing performed per each fs is set to 250 steps, and “processing A” is performed once per each fs. For example, the processing A corresponds to the audio effect processing. As the down-sampling, 200 steps of operations are performed once per 6 fs.
At the present time (which is denoted as “PRESENT” in FIG. 5), 200 steps are secured for the down-sampling, which forms a relatively high processing load so that the processing capacity per each fs does not allow other processing to be performed within the range between 1 fs and 5 fs. This method is advantageous in that it does not need complex processing such as distributed processing, whereas it needs 200 steps per each fs. This reduces the number of steps assigned to other processing per each fs.
A second method is to distribute the number of steps of processing in response to the output timing and is taught in Japanese Unexamined Patent Application Publication No. H09-81542. Suppose that 200 steps of operations adapted to the down-sampling, in which the sampling frequency is reduced from 48 kHz to 8 kHz, are performed so as to produce the output once with 6 fs. In this case, approximately 33 steps are performed per each fs. This method needs intermediate results of operations, which are once stored in an accumulator, to be evacuated to a memory when they are changed with results of other processing. This needs the additional number of steps for realizing the evacuation of data from the accumulator to the memory, and this needs a specific path in the hardware.
FIG. 4 is a block diagram showing the configuration of a conventionally-known digital signal processor, i.e., a DSP 30. The DSP 30 includes an input selector 300, a work RAM 301, a program RAM 302, a multiplier 303, a coefficient RAM 304, an adder/subtracter 305, a selector 306, and a register 307.
In accordance with instructions read from the program RAM 302, digital data (such as digital audio data representing musical tones, speech, etc.) are input into the work RAM 301 via the input selector 300, wherein they are written into an area designated by a prescribed address in the work RAM 301. Then, the digital data are read from the work RAM 301 and are supplied to the multiplier 303. In addition, coefficients used for prescribed processing are read from the coefficient RAM 304 and are supplied to the multiplier 303. The multiplier 303 performs multiplication on the digital data read from the work RAM 301 and the coefficients read from the coefficient RAM 304, so that the multiplication result is supplied to an input terminal X of the adder/subtracter 305. At the initial state, the adder/subtracter 305 does not have values to be added to or subtracted from the multiplication result of the multiplier 303; hence, the multiplication result is directly output from the adder/subtracter 305 and is then supplied to the register 307 via the selector 306. The output of the register 307 is output to an external circuit (not shown) and is also returned to an input terminal Y of the adder/subtracter 305.
Thereafter, next digital data are written into the work RAM 301 via the input selector 300, so that they are read from the work RAM 301 at the prescribed timing and are then supplied to the multiplier 303. In addition, coefficients are read from the coefficient RAM 304. The multiplier 303 performs multiplication on the next digital data read from the work RAM 301 and the coefficients read from the coefficient RAM 304, so that the multiplication result is supplied to the input terminal X of the adder/subtracter 305.
In accordance with an instruction given from the program RAM 302, the adder/subtracter 305 performs an arithmetic operation (corresponding to either addition or subtraction) on the multiplication result of the multiplier 303 and the output of the register 307, so that the arithmetic operation result is supplied to the register 307 via the selector 306. The arithmetic operation result is output to the external circuit (not shown) and is also supplied to the input terminal Y of the adder/subtracter 305.
As described above, a series of arithmetic operations (i.e., multiplication, addition, and subtraction) are sequentially performed every time digital data are input into the input selector 300, thus executing various types of processing such as down-sampling.
The DSP 30 has a single accumulator register (i.e., the register 307); hence, in order to perform plural processings in a time-division manner, it is necessary to evacuate the data of the accumulator register to the memory (i.e., the work RAM 301) every time when down-sampling is completed in each fs; then, it is necessary to return the evacuated data to the accumulator register.
The first method, in which periodically sampled data are processed in such a way that a high processing load is collectively executed in units of periods (each corresponding to fs), is advantageous in that it does not need complex processing such as distributed processing. However, the first method is troublesome because it requires a relatively large number of steps for executing a high processing load in units of periods; and this reduces the number of steps assigned to other processing.
The second method, in which steps are distributed in units of periods in response to output timings, is troublesome because it evacuates intermediate results once stored in the accumulator to the memory every time they are changed with other processing. This needs a considerable number of steps for realizing evacuation of data as well as a specific path in the hardware.